alpaka
Abstraction Library for Parallel Kernel Acceleration
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SyclSubgroupSize.hpp
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1/* Copyright 2023 Andrea Bocci, Aurora Perego
2 * SPDX-License-Identifier: MPL-2.0
3 */
4
5#ifdef ALPAKA_ACC_SYCL_ENABLED
6
7// defines can be taken from
8// https://github.com/llvm/llvm-project/blob/3cfe6aa46e06a8caa3f07057838d31c6ce840076/clang/include/clang/Basic/OffloadArch.h#L18-L28
9
10# ifdef __SYCL_DEVICE_ONLY__
11
12# if /* Broadwell Intel graphics architecture */ \
13 (defined(__SYCL_TARGET_INTEL_GPU_BDW__) && __SYCL_TARGET_INTEL_GPU_BDW__) \
14 || /* Skylake Intel graphics architecture */ \
15 (defined(__SYCL_TARGET_INTEL_GPU_SKL__) && __SYCL_TARGET_INTEL_GPU_SKL__) \
16 || /* Kaby Lake Intel graphics architecture */ \
17 (defined(__SYCL_TARGET_INTEL_GPU_KBL__) && __SYCL_TARGET_INTEL_GPU_KBL__) \
18 || /* Coffee Lake Intel graphics architecture */ \
19 (defined(__SYCL_TARGET_INTEL_GPU_CFL__) && __SYCL_TARGET_INTEL_GPU_CFL__) \
20 || /* Apollo Lake Intel graphics architecture */ \
21 (defined(__SYCL_TARGET_INTEL_GPU_APL__) && __SYCL_TARGET_INTEL_GPU_APL__) \
22 || /* Gemini Lake Intel graphics architecture */ \
23 (defined(__SYCL_TARGET_INTEL_GPU_GLK__) && __SYCL_TARGET_INTEL_GPU_GLK__) \
24 || /* Whiskey Lake Intel graphics architecture */ \
25 (defined(__SYCL_TARGET_INTEL_GPU_WHL__) && __SYCL_TARGET_INTEL_GPU_WHL__) \
26 || /* Amber Lake Intel graphics architecture */ \
27 (defined(__SYCL_TARGET_INTEL_GPU_AML__) && __SYCL_TARGET_INTEL_GPU_AML__) \
28 || /* Comet Lake Intel graphics architecture */ \
29 (defined(__SYCL_TARGET_INTEL_GPU_CML__) && __SYCL_TARGET_INTEL_GPU_CML__) \
30 || /* Ice Lake Intel graphics architecture */ \
31 (defined(__SYCL_TARGET_INTEL_GPU_ICLLP__) && __SYCL_TARGET_INTEL_GPU_ICLLP__) \
32 || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \
33 (defined(__SYCL_TARGET_INTEL_GPU_EHL__) && __SYCL_TARGET_INTEL_GPU_EHL__) \
34 || /* Tiger Lake Intel graphics architecture */ \
35 (defined(__SYCL_TARGET_INTEL_GPU_TGLLP__) && __SYCL_TARGET_INTEL_GPU_TGLLP__) \
36 || /* Rocket Lake Intel graphics architecture */ \
37 (defined(__SYCL_TARGET_INTEL_GPU_RKL__) && __SYCL_TARGET_INTEL_GPU_RKL__) \
38 || /* Alder Lake S or Raptor Lake S Intel graphics architecture */ \
39 (defined(__SYCL_TARGET_INTEL_GPU_ADL_S__) && __SYCL_TARGET_INTEL_GPU_ADL_S__) \
40 || /* Alder Lake P Intel graphics architecture */ \
41 (defined(__SYCL_TARGET_INTEL_GPU_ADL_P__) && __SYCL_TARGET_INTEL_GPU_ADL_P__) \
42 || /* Alder Lake N Intel graphics architecture */ \
43 (defined(__SYCL_TARGET_INTEL_GPU_ADL_N__) && __SYCL_TARGET_INTEL_GPU_ADL_N__) \
44 || /* DG1 Intel graphics architecture */ \
45 (defined(__SYCL_TARGET_INTEL_GPU_DG1__) && __SYCL_TARGET_INTEL_GPU_DG1__) \
46 || /* Alchemist G10 Intel graphics architecture */ \
47 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G10__) && __SYCL_TARGET_INTEL_GPU_ACM_G10__) \
48 || /* Alchemist G11 Intel graphics architecture */ \
49 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G11__) && __SYCL_TARGET_INTEL_GPU_ACM_G11__) \
50 || /* Alchemist G12 Intel graphics architecture */ \
51 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G12__) && __SYCL_TARGET_INTEL_GPU_ACM_G12__) \
52 || /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */ \
53 (defined(__SYCL_TARGET_INTEL_GPU_MTL_U__) && __SYCL_TARGET_INTEL_GPU_MTL_U__) \
54 || /* Meteor Lake H Intel graphics architecture */ \
55 (defined(__SYCL_TARGET_INTEL_GPU_MTL_H__) && __SYCL_TARGET_INTEL_GPU_MTL_H__) \
56 || /* Arrow Lake H Intel graphics architecture */ \
57 (defined(__SYCL_TARGET_INTEL_GPU_ARL_H__) && __SYCL_TARGET_INTEL_GPU_ARL_H__) \
58 || /* Battlemage G21 Intel graphics architecture */ \
59 (defined(__SYCL_TARGET_INTEL_GPU_BMG_G21__) && __SYCL_TARGET_INTEL_GPU_BMG_G21__) \
60 || /* Lunar Lake Intel graphics architecture */ \
61 (defined(__SYCL_TARGET_INTEL_GPU_LNL_M__) && __SYCL_TARGET_INTEL_GPU_LNL_M__)
62
63# define SYCL_SUBGROUP_SIZE (8 | 16 | 32)
64
65# elif /* Ponte Vecchio Intel graphics architecture */ \
66 (defined(__SYCL_TARGET_INTEL_GPU_PVC__) && __SYCL_TARGET_INTEL_GPU_PVC__) \
67 || /* Ponte Vecchio VG Intel graphics architecture */ \
68 (defined(__SYCL_TARGET_INTEL_GPU_PVC_VG__) && __SYCL_TARGET_INTEL_GPU_PVC_VG__)
69
70# define SYCL_SUBGROUP_SIZE (16 | 32)
71
72# elif(/* generate code ahead of time for x86_64 CPUs */ \
73 defined(__SYCL_TARGET_INTEL_X86_64__) && __SYCL_TARGET_INTEL_X86_64__)
74
75# define SYCL_SUBGROUP_SIZE (4 | 8 | 16 | 32 | 64)
76
77# elif /* NVIDIA Maxwell architecture (compute capability 5.0) */ \
78 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_50__) && __SYCL_TARGET_NVIDIA_GPU_SM_50__) \
79 || /* NVIDIA Maxwell architecture (compute capability 5.2) */ \
80 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_52__) && __SYCL_TARGET_NVIDIA_GPU_SM_52__) \
81 || /* NVIDIA Jetson TX1 / Nano (compute capability 5.3) */ \
82 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_53__) && __SYCL_TARGET_NVIDIA_GPU_SM_53__) \
83 || /* NVIDIA Pascal architecture (compute capability 6.0) */ \
84 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_60__) && __SYCL_TARGET_NVIDIA_GPU_SM_60__) \
85 || /* NVIDIA Pascal architecture (compute capability 6.1) */ \
86 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_61__) && __SYCL_TARGET_NVIDIA_GPU_SM_61__) \
87 || /* NVIDIA Jetson TX2 (compute capability 6.2) */ \
88 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_62__) && __SYCL_TARGET_NVIDIA_GPU_SM_62__) \
89 || /* NVIDIA Volta architecture (compute capability 7.0) */ \
90 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_70__) && __SYCL_TARGET_NVIDIA_GPU_SM_70__) \
91 || /* NVIDIA Jetson AGX (compute capability 7.2) */ \
92 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_72__) && __SYCL_TARGET_NVIDIA_GPU_SM_72__) \
93 || /* NVIDIA Turing architecture (compute capability 7.5) */ \
94 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_75__) && __SYCL_TARGET_NVIDIA_GPU_SM_75__) \
95 || /* NVIDIA Ampere architecture (compute capability 8.0) */ \
96 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_80__) && __SYCL_TARGET_NVIDIA_GPU_SM_80__) \
97 || /* NVIDIA Ampere architecture (compute capability 8.6) */ \
98 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_86__) && __SYCL_TARGET_NVIDIA_GPU_SM_86__) \
99 || /* NVIDIA Jetson/Drive AGX Orin (compute capability 8.7) */ \
100 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_87__) && __SYCL_TARGET_NVIDIA_GPU_SM_87__) \
101 || /* NVIDIA Ada Lovelace arch. (compute capability 8.9) */ \
102 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_89__) && __SYCL_TARGET_NVIDIA_GPU_SM_89__) \
103 || /* NVIDIA Hopper architecture (compute capability 9.0) */ \
104 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_90__) && __SYCL_TARGET_NVIDIA_GPU_SM_90__) \
105 || /*NVIDIA Hopper architecture variant(compute capability 9.0a) */ \
106 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_90a__) && __SYCL_TARGET_NVIDIA_GPU_SM_90a__) \
107 || /* NVIDIA Blackwell architecture (compute capability 10.0) */ \
108 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100__) && __SYCL_TARGET_NVIDIA_GPU_SM_100__) \
109 || /* NVIDIA Blackwell architecture variant (compute capability 10.0a) */ \
110 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100a__) && __SYCL_TARGET_NVIDIA_GPU_SM_100a__) \
111 || /* NVIDIA Blackwell Next architecture (compute capability 10.1) */ \
112 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101__) && __SYCL_TARGET_NVIDIA_GPU_SM_101__) \
113 || /* NVIDIA Blackwell Next architecture variant (compute capability 10.1a) */ \
114 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101a__) && __SYCL_TARGET_NVIDIA_GPU_SM_101a__) \
115 || /* NVIDIA Next-generation architecture (compute capability 10.3) */ \
116 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103__) && __SYCL_TARGET_NVIDIA_GPU_SM_103__) \
117 || /* NVIDIA Next-generation architecture variant (compute capability 10.3a) */ \
118 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103a__) && __SYCL_TARGET_NVIDIA_GPU_SM_103a__) \
119 || /* NVIDIA Future architecture (compute capability 12.0) */ \
120 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120__) && __SYCL_TARGET_NVIDIA_GPU_SM_120__) \
121 || /* NVIDIA Future architecture variant (compute capability 12.0a) */ \
122 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120a__) && __SYCL_TARGET_NVIDIA_GPU_SM_120a__) \
123 || /* NVIDIA Future architecture (compute capability 12.1) */ \
124 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121__) && __SYCL_TARGET_NVIDIA_GPU_SM_121__) \
125 || /* NVIDIA Future architecture variant (compute capability 12.1a) */ \
126 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121a__) && __SYCL_TARGET_NVIDIA_GPU_SM_121a__)
127
128# define SYCL_SUBGROUP_SIZE (32) /* CUDA supports warp size 32 */
129
130# elif /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
131 (defined(__SYCL_TARGET_AMD_GPU_GFX700__) && __SYCL_TARGET_AMD_GPU_GFX700__) \
132 || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
133 (defined(__SYCL_TARGET_AMD_GPU_GFX701__) && __SYCL_TARGET_AMD_GPU_GFX701__) \
134 || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
135 (defined(__SYCL_TARGET_AMD_GPU_GFX702__) && __SYCL_TARGET_AMD_GPU_GFX702__) \
136 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
137 (defined(__SYCL_TARGET_AMD_GPU_GFX801__) && __SYCL_TARGET_AMD_GPU_GFX801__) \
138 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
139 (defined(__SYCL_TARGET_AMD_GPU_GFX802__) && __SYCL_TARGET_AMD_GPU_GFX802__) \
140 || /* AMD GCN 4.0 Arctic Islands architecture (gfx 8.0) */ \
141 (defined(__SYCL_TARGET_AMD_GPU_GFX803__) && __SYCL_TARGET_AMD_GPU_GFX803__) \
142 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
143 (defined(__SYCL_TARGET_AMD_GPU_GFX805__) && __SYCL_TARGET_AMD_GPU_GFX805__) \
144 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.1) */ \
145 (defined(__SYCL_TARGET_AMD_GPU_GFX810__) && __SYCL_TARGET_AMD_GPU_GFX810__) \
146 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
147 (defined(__SYCL_TARGET_AMD_GPU_GFX900__) && __SYCL_TARGET_AMD_GPU_GFX900__) \
148 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
149 (defined(__SYCL_TARGET_AMD_GPU_GFX902__) && __SYCL_TARGET_AMD_GPU_GFX902__) \
150 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
151 (defined(__SYCL_TARGET_AMD_GPU_GFX904__) && __SYCL_TARGET_AMD_GPU_GFX904__) \
152 || /* AMD GCN 5.1 Vega II architecture (gfx 9.0) */ \
153 (defined(__SYCL_TARGET_AMD_GPU_GFX906__) && __SYCL_TARGET_AMD_GPU_GFX906__) \
154 || /* AMD CDNA 1.0 Arcturus architecture (gfx 9.0) */ \
155 (defined(__SYCL_TARGET_AMD_GPU_GFX908__) && __SYCL_TARGET_AMD_GPU_GFX908__) \
156 || /* AMD GCN 5.0 Raven 2 architecture (gfx 9.0) */ \
157 (defined(__SYCL_TARGET_AMD_GPU_GFX909__) && __SYCL_TARGET_AMD_GPU_GFX909__) \
158 || /* AMD CDNA 2.0 Aldebaran architecture (gfx 9.0) */ \
159 (defined(__SYCL_TARGET_AMD_GPU_GFX90A__) && __SYCL_TARGET_AMD_GPU_GFX90A__) \
160 || /* AMD GCN 5.1 Renoir architecture (gfx 9.0) */ \
161 (defined(__SYCL_TARGET_AMD_GPU_GFX90C__) && __SYCL_TARGET_AMD_GPU_GFX90C__) \
162 || /* AMD CDNA 3.x generic architecture (gfx 9.4) */ \
163 (defined(__SYCL_TARGET_AMD_GPU_GFX9_4_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX9_4_GENERIC__) \
164 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
165 (defined(__SYCL_TARGET_AMD_GPU_GFX940__) && __SYCL_TARGET_AMD_GPU_GFX940__) \
166 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
167 (defined(__SYCL_TARGET_AMD_GPU_GFX941__) && __SYCL_TARGET_AMD_GPU_GFX941__) \
168 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
169 (defined(__SYCL_TARGET_AMD_GPU_GFX942__) && __SYCL_TARGET_AMD_GPU_GFX942__) \
170 || /* AMD CDNA 3.5 derivative architecture (gfx 9.5) */ \
171 (defined(__SYCL_TARGET_AMD_GPU_GFX950__) && __SYCL_TARGET_AMD_GPU_GFX950__) \
172 || /* AMD GCN 5.x generic architecture (gfx 9.x) */ \
173 (defined(__SYCL_TARGET_AMD_GPU_GFX9_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX9_GENERIC__)
174
175# define SYCL_SUBGROUP_SIZE (64) /* up to gfx9, HIP supports wavefront size 64 */
176
177# elif /* AMD RDNA 1.0 Navi 10 architecture (gfx 10.1) */ \
178 (defined(__SYCL_TARGET_AMD_GPU_GFX1010__) && __SYCL_TARGET_AMD_GPU_GFX1010__) \
179 || /* AMD RDNA 1.0 Navi 12 architecture (gfx 10.1) */ \
180 (defined(__SYCL_TARGET_AMD_GPU_GFX1011__) && __SYCL_TARGET_AMD_GPU_GFX1011__) \
181 || /* AMD RDNA 1.0 Navi 14 architecture (gfx 10.1) */ \
182 (defined(__SYCL_TARGET_AMD_GPU_GFX1012__) && __SYCL_TARGET_AMD_GPU_GFX1012__) \
183 || /* AMD RDNA 2.0 Oberon architecture (gfx 10.1) */ \
184 (defined(__SYCL_TARGET_AMD_GPU_GFX1013__) && __SYCL_TARGET_AMD_GPU_GFX1013__) \
185 || /* AMD RDNA 1.x generic architecture (gfx 10.1) */ \
186 (defined(__SYCL_TARGET_AMD_GPU_GFX10_1_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX10_1_GENERIC__) \
187 || /* AMD RDNA 2.0 Navi 21 architecture (gfx 10.3) */ \
188 (defined(__SYCL_TARGET_AMD_GPU_GFX1030__) && __SYCL_TARGET_AMD_GPU_GFX1030__) \
189 || /* AMD RDNA 2.0 Navi 22 architecture (gfx 10.3) */ \
190 (defined(__SYCL_TARGET_AMD_GPU_GFX1031__) && __SYCL_TARGET_AMD_GPU_GFX1031__) \
191 || /* AMD RDNA 2.0 Navi 23 architecture (gfx 10.3) */ \
192 (defined(__SYCL_TARGET_AMD_GPU_GFX1032__) && __SYCL_TARGET_AMD_GPU_GFX1032__) \
193 || /* AMD RDNA 2.0 Van Gogh architecture (gfx 10.3) */ \
194 (defined(__SYCL_TARGET_AMD_GPU_GFX1033__) && __SYCL_TARGET_AMD_GPU_GFX1033__) \
195 || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \
196 (defined(__SYCL_TARGET_AMD_GPU_GFX1034__) && __SYCL_TARGET_AMD_GPU_GFX1034__) \
197 || /* AMD RDNA 2.0 Rembrandt Mobile architecture (gfx 10.3) */ \
198 (defined(__SYCL_TARGET_AMD_GPU_GFX1035__) && __SYCL_TARGET_AMD_GPU_GFX1035__) \
199 || /* AMD RDNA 2.0 Raphael architecture (gfx 10.3) */ \
200 (defined(__SYCL_TARGET_AMD_GPU_GFX1036__) && __SYCL_TARGET_AMD_GPU_GFX1036__) \
201 || /* AMD RDNA 2.x generic architecture (gfx 10.3) */ \
202 (defined(__SYCL_TARGET_AMD_GPU_GFX10_3_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX10_3_GENERIC__) \
203 || /* AMD RDNA 3.0 Navi 31 architecture (gfx 11.0) */ \
204 (defined(__SYCL_TARGET_AMD_GPU_GFX1100__) && __SYCL_TARGET_AMD_GPU_GFX1100__) \
205 || /* AMD RDNA 3.0 Navi 32 architecture (gfx 11.0) */ \
206 (defined(__SYCL_TARGET_AMD_GPU_GFX1101__) && __SYCL_TARGET_AMD_GPU_GFX1101__) \
207 || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
208 (defined(__SYCL_TARGET_AMD_GPU_GFX1102__) && __SYCL_TARGET_AMD_GPU_GFX1102__) \
209 || /* AMD RDNA 3.0 Phoenix mobile architecture (gfx 11.0) */ \
210 (defined(__SYCL_TARGET_AMD_GPU_GFX1103__) && __SYCL_TARGET_AMD_GPU_GFX1103__) \
211 || /* AMD RDNA 3.x generic architecture (gfx 11.x) */ \
212 (defined(__SYCL_TARGET_AMD_GPU_GFX11_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX11_GENERIC__) \
213 || /* AMD RDNA 3.5 Strix Point architecture (gfx 11.5) */ \
214 (defined(__SYCL_TARGET_AMD_GPU_GFX1150__) && __SYCL_TARGET_AMD_GPU_GFX1150__) \
215 || /* AMD RDNA 3.5 Strix Halo architecture (gfx 11.5) */ \
216 (defined(__SYCL_TARGET_AMD_GPU_GFX1151__) && __SYCL_TARGET_AMD_GPU_GFX1151__) \
217 || /* AMD RDNA 4.0 Navi 44 architecture (gfx 12.0) */ \
218 (defined(__SYCL_TARGET_AMD_GPU_GFX1200__) && __SYCL_TARGET_AMD_GPU_GFX1200__) \
219 || /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */ \
220 (defined(__SYCL_TARGET_AMD_GPU_GFX1201__) && __SYCL_TARGET_AMD_GPU_GFX1201__) \
221 || /* AMD RDNA 4.x generic architecture (gfx 12.x) */ \
222 (defined(__SYCL_TARGET_AMD_GPU_GFX12_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX12_GENERIC__) \
223 || /* AMD RDNA 4.5 derivative architecture (gfx 12.5) */ \
224 (defined(__SYCL_TARGET_AMD_GPU_GFX1250__) && __SYCL_TARGET_AMD_GPU_GFX1250__) \
225 || /* AMD RDNA 4.5 derivative architecture (gfx 12.5) */ \
226 (defined(__SYCL_TARGET_AMD_GPU_GFX1251__) && __SYCL_TARGET_AMD_GPU_GFX1251__)
227
228# define SYCL_SUBGROUP_SIZE (32) /* starting from gfx10, HIP supports wavefront size 32 */
229
230# else // __SYCL_TARGET_*
231
232# define SYCL_SUBGROUP_SIZE (0) /* unknown target */
233
234# endif // __SYCL_TARGET_*
235
236# else
237
238# define SYCL_SUBGROUP_SIZE (0) /* host compilation */
239
240# endif // __SYCL_DEVICE_ONLY__
241
242#endif // ALPAKA_ACC_SYCL_ENABLED