alpaka
Abstraction Library for Parallel Kernel Acceleration
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SyclSubgroupSize.hpp
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1/* Copyright 2023 Andrea Bocci, Aurora Perego, René Widera
2 * SPDX-License-Identifier: MPL-2.0
3 */
4
5#ifdef ALPAKA_ACC_SYCL_ENABLED
6
7/* Device target macros are generated from clang offload architecture names. Source links:
8 * - clang offload architecture wrapper:
9 * https://github.com/llvm/llvm-project/blob/llvmorg-24-init/clang/include/clang/Basic/OffloadArch.h
10 * - Intel SYCL offload architecture list:
11 * https://github.com/intel/llvm/blob/sycl/clang/include/clang/Basic/OffloadArch.h
12 * - NVIDIA target parser list:
13 * https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/TargetParser/NVPTXTargetParser.def
14 * - AMDGPU processor table:
15 * https://llvm.org/docs/AMDGPUUsage.html#processors
16 */
17
18# ifdef __SYCL_DEVICE_ONLY__
19
20# if /* Broadwell Intel graphics architecture */ \
21 (defined(__SYCL_TARGET_INTEL_GPU_BDW__) && __SYCL_TARGET_INTEL_GPU_BDW__) \
22 || /* Skylake Intel graphics architecture */ \
23 (defined(__SYCL_TARGET_INTEL_GPU_SKL__) && __SYCL_TARGET_INTEL_GPU_SKL__) \
24 || /* Kaby Lake Intel graphics architecture */ \
25 (defined(__SYCL_TARGET_INTEL_GPU_KBL__) && __SYCL_TARGET_INTEL_GPU_KBL__) \
26 || /* Coffee Lake Intel graphics architecture */ \
27 (defined(__SYCL_TARGET_INTEL_GPU_CFL__) && __SYCL_TARGET_INTEL_GPU_CFL__) \
28 || /* Apollo Lake Intel graphics architecture */ \
29 (defined(__SYCL_TARGET_INTEL_GPU_APL__) && __SYCL_TARGET_INTEL_GPU_APL__) \
30 || /* Broxton Intel graphics architecture */ \
31 (defined(__SYCL_TARGET_INTEL_GPU_BXT__) && __SYCL_TARGET_INTEL_GPU_BXT__) \
32 || /* Gemini Lake Intel graphics architecture */ \
33 (defined(__SYCL_TARGET_INTEL_GPU_GLK__) && __SYCL_TARGET_INTEL_GPU_GLK__) \
34 || /* Whiskey Lake Intel graphics architecture */ \
35 (defined(__SYCL_TARGET_INTEL_GPU_WHL__) && __SYCL_TARGET_INTEL_GPU_WHL__) \
36 || /* Amber Lake Intel graphics architecture */ \
37 (defined(__SYCL_TARGET_INTEL_GPU_AML__) && __SYCL_TARGET_INTEL_GPU_AML__) \
38 || /* Comet Lake Intel graphics architecture */ \
39 (defined(__SYCL_TARGET_INTEL_GPU_CML__) && __SYCL_TARGET_INTEL_GPU_CML__) \
40 || /* Ice Lake LP Intel graphics architecture */ \
41 (defined(__SYCL_TARGET_INTEL_GPU_ICLLP__) && __SYCL_TARGET_INTEL_GPU_ICLLP__) \
42 || /* Ice Lake Intel graphics architecture */ \
43 (defined(__SYCL_TARGET_INTEL_GPU_ICL__) && __SYCL_TARGET_INTEL_GPU_ICL__) \
44 || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \
45 (defined(__SYCL_TARGET_INTEL_GPU_EHL__) && __SYCL_TARGET_INTEL_GPU_EHL__) \
46 || /* Jasper Lake Intel graphics architecture */ \
47 (defined(__SYCL_TARGET_INTEL_GPU_JSL__) && __SYCL_TARGET_INTEL_GPU_JSL__) \
48 || /* Tiger Lake LP Intel graphics architecture */ \
49 (defined(__SYCL_TARGET_INTEL_GPU_TGLLP__) && __SYCL_TARGET_INTEL_GPU_TGLLP__) \
50 || /* Tiger Lake Intel graphics architecture */ \
51 (defined(__SYCL_TARGET_INTEL_GPU_TGL__) && __SYCL_TARGET_INTEL_GPU_TGL__) \
52 || /* Rocket Lake Intel graphics architecture */ \
53 (defined(__SYCL_TARGET_INTEL_GPU_RKL__) && __SYCL_TARGET_INTEL_GPU_RKL__) \
54 || /* Alder Lake S or Raptor Lake S Intel graphics architecture */ \
55 (defined(__SYCL_TARGET_INTEL_GPU_ADL_S__) && __SYCL_TARGET_INTEL_GPU_ADL_S__) \
56 || /* Raptor Lake S Intel graphics architecture */ \
57 (defined(__SYCL_TARGET_INTEL_GPU_RPL_S__) && __SYCL_TARGET_INTEL_GPU_RPL_S__) \
58 || /* Alder Lake P Intel graphics architecture */ \
59 (defined(__SYCL_TARGET_INTEL_GPU_ADL_P__) && __SYCL_TARGET_INTEL_GPU_ADL_P__) \
60 || /* Alder Lake N Intel graphics architecture */ \
61 (defined(__SYCL_TARGET_INTEL_GPU_ADL_N__) && __SYCL_TARGET_INTEL_GPU_ADL_N__) \
62 || /* DG1 Intel graphics architecture */ \
63 (defined(__SYCL_TARGET_INTEL_GPU_DG1__) && __SYCL_TARGET_INTEL_GPU_DG1__) \
64 || /* DG2 Intel graphics architecture */ \
65 (defined(__SYCL_TARGET_INTEL_GPU_DG2__) && __SYCL_TARGET_INTEL_GPU_DG2__) \
66 || /* Alchemist G10 Intel graphics architecture */ \
67 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G10__) && __SYCL_TARGET_INTEL_GPU_ACM_G10__) \
68 || /* DG2 G10 Intel graphics architecture */ \
69 (defined(__SYCL_TARGET_INTEL_GPU_DG2_G10__) && __SYCL_TARGET_INTEL_GPU_DG2_G10__) \
70 || /* Alchemist G11 Intel graphics architecture */ \
71 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G11__) && __SYCL_TARGET_INTEL_GPU_ACM_G11__) \
72 || /* DG2 G11 Intel graphics architecture */ \
73 (defined(__SYCL_TARGET_INTEL_GPU_DG2_G11__) && __SYCL_TARGET_INTEL_GPU_DG2_G11__) \
74 || /* Alchemist G12 Intel graphics architecture */ \
75 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G12__) && __SYCL_TARGET_INTEL_GPU_ACM_G12__) \
76 || /* DG2 G12 Intel graphics architecture */ \
77 (defined(__SYCL_TARGET_INTEL_GPU_DG2_G12__) && __SYCL_TARGET_INTEL_GPU_DG2_G12__) \
78 || /* Meteor Lake Intel graphics architecture */ \
79 (defined(__SYCL_TARGET_INTEL_GPU_MTL__) && __SYCL_TARGET_INTEL_GPU_MTL__) \
80 || /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */ \
81 (defined(__SYCL_TARGET_INTEL_GPU_MTL_U__) && __SYCL_TARGET_INTEL_GPU_MTL_U__) \
82 || /* Meteor Lake S Intel graphics architecture */ \
83 (defined(__SYCL_TARGET_INTEL_GPU_MTL_S__) && __SYCL_TARGET_INTEL_GPU_MTL_S__) \
84 || /* Arrow Lake U Intel graphics architecture */ \
85 (defined(__SYCL_TARGET_INTEL_GPU_ARL_U__) && __SYCL_TARGET_INTEL_GPU_ARL_U__) \
86 || /* Arrow Lake S Intel graphics architecture */ \
87 (defined(__SYCL_TARGET_INTEL_GPU_ARL_S__) && __SYCL_TARGET_INTEL_GPU_ARL_S__) \
88 || /* Meteor Lake H Intel graphics architecture */ \
89 (defined(__SYCL_TARGET_INTEL_GPU_MTL_H__) && __SYCL_TARGET_INTEL_GPU_MTL_H__) \
90 || /* Arrow Lake H Intel graphics architecture */ \
91 (defined(__SYCL_TARGET_INTEL_GPU_ARL_H__) && __SYCL_TARGET_INTEL_GPU_ARL_H__) \
92 || /* Battlemage Intel graphics architecture */ \
93 (defined(__SYCL_TARGET_INTEL_GPU_BMG__) && __SYCL_TARGET_INTEL_GPU_BMG__) \
94 || /* Battlemage G21 Intel graphics architecture */ \
95 (defined(__SYCL_TARGET_INTEL_GPU_BMG_G21__) && __SYCL_TARGET_INTEL_GPU_BMG_G21__) \
96 || /* Battlemage G31 Intel graphics architecture */ \
97 (defined(__SYCL_TARGET_INTEL_GPU_BMG_G31__) && __SYCL_TARGET_INTEL_GPU_BMG_G31__) \
98 || /* Panther Lake Intel graphics architecture */ \
99 (defined(__SYCL_TARGET_INTEL_GPU_PTL__) && __SYCL_TARGET_INTEL_GPU_PTL__) \
100 || /* Lunar Lake Intel graphics architecture */ \
101 (defined(__SYCL_TARGET_INTEL_GPU_LNL_M__) && __SYCL_TARGET_INTEL_GPU_LNL_M__) \
102 || /* Panther Lake H Intel graphics architecture */ \
103 (defined(__SYCL_TARGET_INTEL_GPU_PTL_H__) && __SYCL_TARGET_INTEL_GPU_PTL_H__) \
104 || /* Panther Lake U Intel graphics architecture */ \
105 (defined(__SYCL_TARGET_INTEL_GPU_PTL_U__) && __SYCL_TARGET_INTEL_GPU_PTL_U__) \
106 || /* Wildcat Lake Intel graphics architecture */ \
107 (defined(__SYCL_TARGET_INTEL_GPU_WCL__) && __SYCL_TARGET_INTEL_GPU_WCL__) \
108 || /* Nova Lake S Intel graphics architecture */ \
109 (defined(__SYCL_TARGET_INTEL_GPU_NVL_S__) && __SYCL_TARGET_INTEL_GPU_NVL_S__) \
110 || /* Nova Lake U Intel graphics architecture */ \
111 (defined(__SYCL_TARGET_INTEL_GPU_NVL_U__) && __SYCL_TARGET_INTEL_GPU_NVL_U__) \
112 || /* Nova Lake P Intel graphics architecture */ \
113 (defined(__SYCL_TARGET_INTEL_GPU_NVL_P__) && __SYCL_TARGET_INTEL_GPU_NVL_P__) \
114 || /* Crescent Island Intel graphics architecture */ \
115 (defined(__SYCL_TARGET_INTEL_GPU_CRI__) && __SYCL_TARGET_INTEL_GPU_CRI__)
116
117# define SYCL_SUBGROUP_SIZE (8 | 16 | 32)
118
119# elif /* Ponte Vecchio Intel graphics architecture */ \
120 (defined(__SYCL_TARGET_INTEL_GPU_PVC__) && __SYCL_TARGET_INTEL_GPU_PVC__) \
121 || /* Ponte Vecchio VG Intel graphics architecture */ \
122 (defined(__SYCL_TARGET_INTEL_GPU_PVC_VG__) && __SYCL_TARGET_INTEL_GPU_PVC_VG__)
123
124# define SYCL_SUBGROUP_SIZE (16 | 32)
125
126# elif(/* generate code ahead of time for x86_64 CPUs */ \
127 defined(__SYCL_TARGET_INTEL_X86_64__) && __SYCL_TARGET_INTEL_X86_64__)
128
129# define SYCL_SUBGROUP_SIZE (4 | 8 | 16 | 32 | 64)
130
131# elif /* NVIDIA Maxwell architecture (compute capability 5.0) */ \
132 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_50__) && __SYCL_TARGET_NVIDIA_GPU_SM_50__) \
133 || /* NVIDIA Maxwell architecture (compute capability 5.2) */ \
134 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_52__) && __SYCL_TARGET_NVIDIA_GPU_SM_52__) \
135 || /* NVIDIA Jetson TX1 / Nano (compute capability 5.3) */ \
136 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_53__) && __SYCL_TARGET_NVIDIA_GPU_SM_53__) \
137 || /* NVIDIA Pascal architecture (compute capability 6.0) */ \
138 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_60__) && __SYCL_TARGET_NVIDIA_GPU_SM_60__) \
139 || /* NVIDIA Pascal architecture (compute capability 6.1) */ \
140 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_61__) && __SYCL_TARGET_NVIDIA_GPU_SM_61__) \
141 || /* NVIDIA Jetson TX2 (compute capability 6.2) */ \
142 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_62__) && __SYCL_TARGET_NVIDIA_GPU_SM_62__) \
143 || /* NVIDIA Volta architecture (compute capability 7.0) */ \
144 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_70__) && __SYCL_TARGET_NVIDIA_GPU_SM_70__) \
145 || /* NVIDIA Jetson AGX (compute capability 7.2) */ \
146 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_72__) && __SYCL_TARGET_NVIDIA_GPU_SM_72__) \
147 || /* NVIDIA Turing architecture (compute capability 7.5) */ \
148 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_75__) && __SYCL_TARGET_NVIDIA_GPU_SM_75__) \
149 || /* NVIDIA Ampere architecture (compute capability 8.0) */ \
150 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_80__) && __SYCL_TARGET_NVIDIA_GPU_SM_80__) \
151 || /* NVIDIA Ampere architecture (compute capability 8.6) */ \
152 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_86__) && __SYCL_TARGET_NVIDIA_GPU_SM_86__) \
153 || /* NVIDIA Jetson/Drive AGX Orin (compute capability 8.7) */ \
154 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_87__) && __SYCL_TARGET_NVIDIA_GPU_SM_87__) \
155 || /* NVIDIA architecture (compute capability 8.8) */ \
156 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_88__) && __SYCL_TARGET_NVIDIA_GPU_SM_88__) \
157 || /* NVIDIA Ada Lovelace arch. (compute capability 8.9) */ \
158 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_89__) && __SYCL_TARGET_NVIDIA_GPU_SM_89__) \
159 || /* NVIDIA Hopper architecture (compute capability 9.0) */ \
160 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_90__) && __SYCL_TARGET_NVIDIA_GPU_SM_90__) \
161 || /*NVIDIA Hopper architecture variant(compute capability 9.0a) */ \
162 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_90a__) && __SYCL_TARGET_NVIDIA_GPU_SM_90a__) \
163 || /* NVIDIA Blackwell architecture (compute capability 10.0) */ \
164 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100__) && __SYCL_TARGET_NVIDIA_GPU_SM_100__) \
165 || /* NVIDIA Blackwell architecture variant (compute capability 10.0a) */ \
166 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100a__) && __SYCL_TARGET_NVIDIA_GPU_SM_100a__) \
167 || /* NVIDIA Blackwell architecture family-specific variant (compute capability 10.0f) */ \
168 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100f__) && __SYCL_TARGET_NVIDIA_GPU_SM_100f__) \
169 || /* NVIDIA Blackwell Next architecture (compute capability 10.1) */ \
170 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101__) && __SYCL_TARGET_NVIDIA_GPU_SM_101__) \
171 || /* NVIDIA Blackwell Next architecture variant (compute capability 10.1a) */ \
172 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101a__) && __SYCL_TARGET_NVIDIA_GPU_SM_101a__) \
173 || /* NVIDIA Blackwell Next architecture family-specific variant (compute capability 10.1f) */ \
174 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101f__) && __SYCL_TARGET_NVIDIA_GPU_SM_101f__) \
175 || /* NVIDIA Next-generation architecture (compute capability 10.3) */ \
176 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103__) && __SYCL_TARGET_NVIDIA_GPU_SM_103__) \
177 || /* NVIDIA Next-generation architecture variant (compute capability 10.3a) */ \
178 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103a__) && __SYCL_TARGET_NVIDIA_GPU_SM_103a__) \
179 || /* NVIDIA Next-generation architecture family-specific variant (compute capability 10.3f) */ \
180 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103f__) && __SYCL_TARGET_NVIDIA_GPU_SM_103f__) \
181 || /* NVIDIA Next-generation architecture (compute capability 10.7) */ \
182 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_107__) && __SYCL_TARGET_NVIDIA_GPU_SM_107__) \
183 || /* NVIDIA Next-generation architecture variant (compute capability 10.7a) */ \
184 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_107a__) && __SYCL_TARGET_NVIDIA_GPU_SM_107a__) \
185 || /* NVIDIA Next-generation architecture family-specific variant (compute capability 10.7f) */ \
186 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_107f__) && __SYCL_TARGET_NVIDIA_GPU_SM_107f__) \
187 || /* NVIDIA Next-generation architecture (compute capability 11.0) */ \
188 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_110__) && __SYCL_TARGET_NVIDIA_GPU_SM_110__) \
189 || /* NVIDIA Next-generation architecture variant (compute capability 11.0a) */ \
190 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_110a__) && __SYCL_TARGET_NVIDIA_GPU_SM_110a__) \
191 || /* NVIDIA Next-generation architecture family-specific variant (compute capability 11.0f) */ \
192 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_110f__) && __SYCL_TARGET_NVIDIA_GPU_SM_110f__) \
193 || /* NVIDIA Future architecture (compute capability 12.0) */ \
194 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120__) && __SYCL_TARGET_NVIDIA_GPU_SM_120__) \
195 || /* NVIDIA Future architecture variant (compute capability 12.0a) */ \
196 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120a__) && __SYCL_TARGET_NVIDIA_GPU_SM_120a__) \
197 || /* NVIDIA Future architecture family-specific variant (compute capability 12.0f) */ \
198 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120f__) && __SYCL_TARGET_NVIDIA_GPU_SM_120f__) \
199 || /* NVIDIA Future architecture (compute capability 12.1) */ \
200 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121__) && __SYCL_TARGET_NVIDIA_GPU_SM_121__) \
201 || /* NVIDIA Future architecture variant (compute capability 12.1a) */ \
202 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121a__) && __SYCL_TARGET_NVIDIA_GPU_SM_121a__) \
203 || /* NVIDIA Future architecture family-specific variant (compute capability 12.1f) */ \
204 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121f__) && __SYCL_TARGET_NVIDIA_GPU_SM_121f__)
205
206# define SYCL_SUBGROUP_SIZE (32) /* CUDA supports warp size 32 */
207
208# elif /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
209 (defined(__SYCL_TARGET_AMD_GPU_GFX700__) && __SYCL_TARGET_AMD_GPU_GFX700__) \
210 || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
211 (defined(__SYCL_TARGET_AMD_GPU_GFX701__) && __SYCL_TARGET_AMD_GPU_GFX701__) \
212 || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
213 (defined(__SYCL_TARGET_AMD_GPU_GFX702__) && __SYCL_TARGET_AMD_GPU_GFX702__) \
214 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
215 (defined(__SYCL_TARGET_AMD_GPU_GFX801__) && __SYCL_TARGET_AMD_GPU_GFX801__) \
216 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
217 (defined(__SYCL_TARGET_AMD_GPU_GFX802__) && __SYCL_TARGET_AMD_GPU_GFX802__) \
218 || /* AMD GCN 4.0 Arctic Islands architecture (gfx 8.0) */ \
219 (defined(__SYCL_TARGET_AMD_GPU_GFX803__) && __SYCL_TARGET_AMD_GPU_GFX803__) \
220 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
221 (defined(__SYCL_TARGET_AMD_GPU_GFX805__) && __SYCL_TARGET_AMD_GPU_GFX805__) \
222 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.1) */ \
223 (defined(__SYCL_TARGET_AMD_GPU_GFX810__) && __SYCL_TARGET_AMD_GPU_GFX810__) \
224 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
225 (defined(__SYCL_TARGET_AMD_GPU_GFX900__) && __SYCL_TARGET_AMD_GPU_GFX900__) \
226 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
227 (defined(__SYCL_TARGET_AMD_GPU_GFX902__) && __SYCL_TARGET_AMD_GPU_GFX902__) \
228 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
229 (defined(__SYCL_TARGET_AMD_GPU_GFX904__) && __SYCL_TARGET_AMD_GPU_GFX904__) \
230 || /* AMD GCN 5.1 Vega II architecture (gfx 9.0) */ \
231 (defined(__SYCL_TARGET_AMD_GPU_GFX906__) && __SYCL_TARGET_AMD_GPU_GFX906__) \
232 || /* AMD CDNA 1.0 Arcturus architecture (gfx 9.0) */ \
233 (defined(__SYCL_TARGET_AMD_GPU_GFX908__) && __SYCL_TARGET_AMD_GPU_GFX908__) \
234 || /* AMD GCN 5.0 Raven 2 architecture (gfx 9.0) */ \
235 (defined(__SYCL_TARGET_AMD_GPU_GFX909__) && __SYCL_TARGET_AMD_GPU_GFX909__) \
236 || /* AMD CDNA 2.0 Aldebaran architecture (gfx 9.0) */ \
237 (defined(__SYCL_TARGET_AMD_GPU_GFX90A__) && __SYCL_TARGET_AMD_GPU_GFX90A__) \
238 || /* AMD GCN 5.1 Renoir architecture (gfx 9.0) */ \
239 (defined(__SYCL_TARGET_AMD_GPU_GFX90C__) && __SYCL_TARGET_AMD_GPU_GFX90C__) \
240 || /* AMD CDNA 3.x generic architecture (gfx 9.4) */ \
241 (defined(__SYCL_TARGET_AMD_GPU_GFX9_4_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX9_4_GENERIC__) \
242 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
243 (defined(__SYCL_TARGET_AMD_GPU_GFX940__) && __SYCL_TARGET_AMD_GPU_GFX940__) \
244 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
245 (defined(__SYCL_TARGET_AMD_GPU_GFX941__) && __SYCL_TARGET_AMD_GPU_GFX941__) \
246 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
247 (defined(__SYCL_TARGET_AMD_GPU_GFX942__) && __SYCL_TARGET_AMD_GPU_GFX942__) \
248 || /* AMD CDNA 4.0 derivative architecture (gfx 9.5) */ \
249 (defined(__SYCL_TARGET_AMD_GPU_GFX950__) && __SYCL_TARGET_AMD_GPU_GFX950__) \
250 || /* AMD GCN 5.x generic architecture (gfx 9.x) */ \
251 (defined(__SYCL_TARGET_AMD_GPU_GFX9_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX9_GENERIC__)
252
253# define SYCL_SUBGROUP_SIZE (64) /* up to gfx9, HIP supports wavefront size 64 */
254
255# elif /* AMD RDNA 1.0 Navi 10 architecture (gfx 10.1) */ \
256 (defined(__SYCL_TARGET_AMD_GPU_GFX1010__) && __SYCL_TARGET_AMD_GPU_GFX1010__) \
257 || /* AMD RDNA 1.0 Navi 12 architecture (gfx 10.1) */ \
258 (defined(__SYCL_TARGET_AMD_GPU_GFX1011__) && __SYCL_TARGET_AMD_GPU_GFX1011__) \
259 || /* AMD RDNA 1.0 Navi 14 architecture (gfx 10.1) */ \
260 (defined(__SYCL_TARGET_AMD_GPU_GFX1012__) && __SYCL_TARGET_AMD_GPU_GFX1012__) \
261 || /* AMD RDNA 2.0 Oberon architecture (gfx 10.1) */ \
262 (defined(__SYCL_TARGET_AMD_GPU_GFX1013__) && __SYCL_TARGET_AMD_GPU_GFX1013__) \
263 || /* AMD RDNA 1.x generic architecture (gfx 10.1) */ \
264 (defined(__SYCL_TARGET_AMD_GPU_GFX10_1_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX10_1_GENERIC__) \
265 || /* AMD RDNA 2.0 Navi 21 architecture (gfx 10.3) */ \
266 (defined(__SYCL_TARGET_AMD_GPU_GFX1030__) && __SYCL_TARGET_AMD_GPU_GFX1030__) \
267 || /* AMD RDNA 2.0 Navi 22 architecture (gfx 10.3) */ \
268 (defined(__SYCL_TARGET_AMD_GPU_GFX1031__) && __SYCL_TARGET_AMD_GPU_GFX1031__) \
269 || /* AMD RDNA 2.0 Navi 23 architecture (gfx 10.3) */ \
270 (defined(__SYCL_TARGET_AMD_GPU_GFX1032__) && __SYCL_TARGET_AMD_GPU_GFX1032__) \
271 || /* AMD RDNA 2.0 Van Gogh architecture (gfx 10.3) */ \
272 (defined(__SYCL_TARGET_AMD_GPU_GFX1033__) && __SYCL_TARGET_AMD_GPU_GFX1033__) \
273 || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \
274 (defined(__SYCL_TARGET_AMD_GPU_GFX1034__) && __SYCL_TARGET_AMD_GPU_GFX1034__) \
275 || /* AMD RDNA 2.0 Rembrandt Mobile architecture (gfx 10.3) */ \
276 (defined(__SYCL_TARGET_AMD_GPU_GFX1035__) && __SYCL_TARGET_AMD_GPU_GFX1035__) \
277 || /* AMD RDNA 2.0 Raphael architecture (gfx 10.3) */ \
278 (defined(__SYCL_TARGET_AMD_GPU_GFX1036__) && __SYCL_TARGET_AMD_GPU_GFX1036__) \
279 || /* AMD RDNA 2.x generic architecture (gfx 10.3) */ \
280 (defined(__SYCL_TARGET_AMD_GPU_GFX10_3_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX10_3_GENERIC__) \
281 || /* AMD RDNA 3.0 Navi 31 architecture (gfx 11.0) */ \
282 (defined(__SYCL_TARGET_AMD_GPU_GFX1100__) && __SYCL_TARGET_AMD_GPU_GFX1100__) \
283 || /* AMD RDNA 3.0 Navi 32 architecture (gfx 11.0) */ \
284 (defined(__SYCL_TARGET_AMD_GPU_GFX1101__) && __SYCL_TARGET_AMD_GPU_GFX1101__) \
285 || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
286 (defined(__SYCL_TARGET_AMD_GPU_GFX1102__) && __SYCL_TARGET_AMD_GPU_GFX1102__) \
287 || /* AMD RDNA 3.0 Phoenix mobile architecture (gfx 11.0) */ \
288 (defined(__SYCL_TARGET_AMD_GPU_GFX1103__) && __SYCL_TARGET_AMD_GPU_GFX1103__) \
289 || /* AMD RDNA 3.x generic architecture (gfx 11.x) */ \
290 (defined(__SYCL_TARGET_AMD_GPU_GFX11_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX11_GENERIC__) \
291 || /* AMD RDNA 3.5 Strix Point architecture (gfx 11.5) */ \
292 (defined(__SYCL_TARGET_AMD_GPU_GFX1150__) && __SYCL_TARGET_AMD_GPU_GFX1150__) \
293 || /* AMD RDNA 3.5 Strix Halo architecture (gfx 11.5) */ \
294 (defined(__SYCL_TARGET_AMD_GPU_GFX1151__) && __SYCL_TARGET_AMD_GPU_GFX1151__) \
295 || /* AMD RDNA 3.5 Krackan Point architecture (gfx 11.5) */ \
296 (defined(__SYCL_TARGET_AMD_GPU_GFX1152__) && __SYCL_TARGET_AMD_GPU_GFX1152__) \
297 || /* AMD RDNA 3.5 derivative architecture (gfx 11.5) */ \
298 (defined(__SYCL_TARGET_AMD_GPU_GFX1153__) && __SYCL_TARGET_AMD_GPU_GFX1153__) \
299 || /* AMD RDNA 3.5 derivative architecture (gfx 11.5) */ \
300 (defined(__SYCL_TARGET_AMD_GPU_GFX1154__) && __SYCL_TARGET_AMD_GPU_GFX1154__) \
301 || /* AMD RDNA 4m generic architecture (gfx 11.7) */ \
302 (defined(__SYCL_TARGET_AMD_GPU_GFX11_7_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX11_7_GENERIC__) \
303 || /* AMD RDNA 4m derivative architecture (gfx 11.7) */ \
304 (defined(__SYCL_TARGET_AMD_GPU_GFX1170__) && __SYCL_TARGET_AMD_GPU_GFX1170__) \
305 || /* AMD RDNA 4m derivative architecture (gfx 11.7) */ \
306 (defined(__SYCL_TARGET_AMD_GPU_GFX1171__) && __SYCL_TARGET_AMD_GPU_GFX1171__) \
307 || /* AMD RDNA 4m derivative architecture (gfx 11.7) */ \
308 (defined(__SYCL_TARGET_AMD_GPU_GFX1172__) && __SYCL_TARGET_AMD_GPU_GFX1172__) \
309 || /* AMD RDNA 4.0 Navi 44 architecture (gfx 12.0) */ \
310 (defined(__SYCL_TARGET_AMD_GPU_GFX1200__) && __SYCL_TARGET_AMD_GPU_GFX1200__) \
311 || /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */ \
312 (defined(__SYCL_TARGET_AMD_GPU_GFX1201__) && __SYCL_TARGET_AMD_GPU_GFX1201__) \
313 || /* AMD RDNA 4.x generic architecture (gfx 12.x) */ \
314 (defined(__SYCL_TARGET_AMD_GPU_GFX12_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX12_GENERIC__) \
315 || /* AMD RDNA 4.5 generic architecture (gfx 12.5) */ \
316 (defined(__SYCL_TARGET_AMD_GPU_GFX12_5_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX12_5_GENERIC__) \
317 || /* AMD RDNA 4.5 derivative architecture (gfx 12.5) */ \
318 (defined(__SYCL_TARGET_AMD_GPU_GFX1250__) && __SYCL_TARGET_AMD_GPU_GFX1250__) \
319 || /* AMD RDNA 4.5 derivative architecture (gfx 12.5) */ \
320 (defined(__SYCL_TARGET_AMD_GPU_GFX1251__) && __SYCL_TARGET_AMD_GPU_GFX1251__) \
321 || /* AMD RDNA 5.0 generic architecture (gfx 13.x) */ \
322 (defined(__SYCL_TARGET_AMD_GPU_GFX13_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX13_GENERIC__) \
323 || /* AMD RDNA 5.0 derivative architecture (gfx 13.1) */ \
324 (defined(__SYCL_TARGET_AMD_GPU_GFX1310__) && __SYCL_TARGET_AMD_GPU_GFX1310__)
325
326# define SYCL_SUBGROUP_SIZE (32) /* starting from gfx10, HIP supports wavefront size 32 */
327
328# else // __SYCL_TARGET_*
329
330# define SYCL_SUBGROUP_SIZE (0) /* unknown target */
331
332# endif // __SYCL_TARGET_*
333
334# else
335
336# define SYCL_SUBGROUP_SIZE (0) /* host compilation */
337
338# endif // __SYCL_DEVICE_ONLY__
339
340#endif // ALPAKA_ACC_SYCL_ENABLED